DDR3/4 Clearance – Highly Competitive Prices, Immediate Delivery

June 11, 2025

Recently, the DDR3/4 market has undergone a sudden change, falling into a tense situation of shortage and price increase. Major global DRAM manufacturers Samsung, Micron, and SK Hynix plan to gradually discontinue DDR3 and DDR4, shifting their focus to higher profit DDR5 and HBM products. This decision led to a sharp decrease in the supply of DDR3/4 in the market, causing a surge in spot market prices. Our company has reserved a batch of DDR3/4 in advance with keen market insight.

The following DDR models are in stock with genuine quality assurance:

DDR3/4
Product Name	Product Mode	Spec	Code	Brand	Quantity	Warehouse
DDR3L 256MB16	A3T4GF40BBF-HP	DDR3L 4Gb16 1866	6643-107	PG/ZENTEL	46670	Shenzhen

DDR3L 256MB16	A3T4GF40BBF-HP	DDR3L 4Gb16 1866	6643-107	PG/ZENTEL	938410	HongKong

DDR4 512MB16	A3F8GH40BBF-KDPR	DDR4 8Gb16 2666	7634-075	PG/ZENTEL	14210	Shenzhen

DDR4 512MB16	A3F8GH40BBF-KDPR	DDR4 8Gb16 2666	7634-075	PG/ZENTEL	238260	HongKong

8Gb(DDR) 256M x32	NT6AN256T32AV-J2	LPDDR4-3733		PG/Nanya	35K

8Gb DDR4 SDRAM Specification

• Power supply

-VDD = VDDQ = 1.2V 5%

-VPP = 2.5V –5% + 10%

• Data rate
- 3200 Mbps (DDR4-3200)
- 2933 Mbps (DDR4-2933)
- 2666 Mbps (DDR4-2666)
- 2400 Mbps (DDR4-2400)
- 2133 Mbps (DDR4-2133)
- 1866 Mbps (DDR4-1866)
- 1600 Mbps (DDR4-1600)
• Package
- 96-ball FBGA (A3F8GH40BBF)
- Lead-free
• 8 internal banks2 groups of 4 banks each (x16)
• Differential clock inputs operation (CK_t and CK_c)
• Bi-directional differential data strobe (DQS_t andDQS_c)
• Asynchronous reset is supported (RESET_n)
• ZQ calibration for Output driver by compare to
external reference resistance

(RZQ 240 ohm 1%)

• Nominal, park and dynamic On-die Termination (ODT)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge
• CAS Latency (CL): 13, 15, 17, 19, 21, and 22 supported
• Additive Latency (AL) 0, CL-1, and CL-2 supported
• Burst Length (BL): 8 and 4 with on the fly supported
• CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16, 18,
and 20 supported
• Operating case temperature range

TC = 0C to+95C(Commercial grade)

• Refresh cycles
Average refresh period

7.8s at 0C TC +85C

3.9s at +85C < TC +95C
• Fine granularity refresh is supported
• Adjustable internal generation VREFDQ
• Pseudo Open Drain (POD) interface for data input/output
• Drive strength selected by MRS
• The high-speed data transfer by the 8 bits pre-fetch
• Temperature Controlled Refresh (TCR) mode is supported
• Low Power Auto Self Refresh (LPASR) mode is supported
• Self refresh abort is supported
• Programmable preamble is supported
• Write leveling is supported
• Command/Address latency (CAL) is supported
• Multipurpose register READ and WRITEcapability
• Command Address Parity (CA Parity) for
command address signal error detect and inform it
to controller
• Write Cyclic Redundancy Code (CRC) for DQ error
detect and inform it to controller during high-speed
operation
• Data Bus Inversion (DBI) for Improve the power
consumption and signal integrity of the memory
interface
• Data mask (DM) for write data
• Per DRAM Addressability (PDA) for each DRAM
can be set a different mode register value
individually and has individual adjustment
• Gear down mode (1/2 and 1/4 rate) is supported
• hPPR and sPPR is supported
• Connectivity test (x16 only)
• Maximum power down mode for the lowest power
consumption with no internal refresh activity
• JEDEC JESD-79-4 compliant

4Gb DDR3/DDR3L SDRAM Specification
Specifications	Features
• Density: 4G bits • Organization o 8 banks x 64M words x 8 bits o 8 banks x 32M words x 16 bits • Package o 78-ball FBGA o 96-ball FBGA • Power supply: -HP o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) o Backward compatible with DDR3 operation VDD, VDDQ = 1.5 V (1.425 to 1.575 V) -JR o VDD, VDDQ = 1.5 V (1.425 to 1.575 V) -JRL o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) • Data Rate: 1866 Mbps/2133 Mbps (max.) • 1KB page size (x8) o Row address: AX0 to AX15 o Column address: AY0 to AY9 • 2KB page size (x16) o Row address: AX0 to AX14 o Column address: AY0 to AY9 • Eight internal banks for concurrent operation • Burst lengths(BL): 8 and 4 with Burst Chop(BC) • Burst type(BT) o Sequential (8, 4 with BC) o Interleave (8, 4 with BC) • CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14 • CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10 • Precharge: auto precharge option for each burst access • Driver strength: RZQ/7, RZQ/6 (RZQ = 240 Ω) • Refresh: auto-refresh, self-refresh • Average refresh period o 7.8 us at TC ≤ +85℃ o 3.9 us at TC > +85℃ • Operating temperature range o TC = 0°C to +95°C (Commercial grade) o TC = -40°C to +95°C (Industrial grade) o TC = -40°C to +105°C (Automotive grade 2)	• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Double data-rate architecture: two data transfers per clock cycle • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted CAS by programmable additive latency for better command and data bus efficiency • On-Die Termination (ODT) for better signal quality o  Synchronous ODT o  Dynamic ODT o  Asynchronous ODT • Multi Purpose Register (MPR) for pre-defined pattern read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • RESET pin for Power-up sequence and reset function • SRT(Self Refresh Temperature) range: o Normal/Extended • Auto Self-Refresh (ASR) • Programmable output driver impedance control • JEDEC compliant DDR3/DDR3L • Row-Hammer-Free (RH-Free): detection/blocking circuit inside

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If you have purchasing needs for DDR3/4 , please feel free to contact our sales team!

Contact Person :	Ms. Sunny Wu
Tel :	+8615712055204